

Hi everyone,
I'm currently working through the first project and have so far constructed the Not, And, Or, and Xor gates.
I spent a good 6 hours to get to this point and quite frankly, I'm still baffled about how to actually design the gates.
I understand what each gate does and also understand how the gates function once I see the solution, but my brain cannot comprehend on how to get to the answers in the first place.
For example, I could not figure out how to design the Xor gate without help. Now that I'm working on the Mux gate, I'm even more confused. Is there something I'm missing here?
I appreciate any advice and help.
Thanks!

Administrator

One way to design this kind of logic is to build a truth table. Once you have the Not, And, and Or gates available, you can then always build up a circuit that implements that truth table  it may not be pretty and it may not be efficient, but it will work.
Let's make up a gate that has the following truth table for two inputs, A and B, and one output, Y.
A B Y
0 0 1
0 1 1
1 0 0
1 1 1
Go line by line and for each line that the output is supposed to be a 1, you create a circuit that produces a 1 for that set of input conditions. For the first row, we need A to be LO and B to be LO. This is just another way of saying that we need:
[(Not A) to be HI] And [(Not B) to be HI]
or just
(Not A) And (Not B)
We can then add the corresponding logic for each row that needs a HI output.
A B Y
0 0 1 (Not A) And (Not B)
0 1 1 (Not A) And (B)
1 0 0
1 1 1 (A) And (B)
Now we just need to Or all of these together. Since we have three signals but only a 2input Or gate, we need to layer them using the following knowledge
X Or Y Or Z = (X Or Y) Or (Z)
So we now have the following logic:
{[(Not A) And (Not B)] Or [(Not A) And (B)]} Or [(A) And (B)]
Now it's just a matter of wiring this up in HDL code

